1. Field of the Invention
The present invention relates to a semiconductor storage device mounted on an IC card or the like and particularly to a technique for eliminating a through current generated upon operation and reducing a peak current.
2. Description of the Related Art
A semiconductor storage device is strictly requested for its low consumed power. Particularly, in the semiconductor storage device mounted on the IC card or the like, the increase of peak current or consumed current upon operation may possibly result in a problem of malfunction due to the heat generation of the IC card or the sudden fall of source voltage. In recent years, it has been an important problem to reduce the peak current or to reduce the consumed current.
As a usual semiconductor storage device, an EEPROM (a nonvolatile memory capable of being electrically erased or programmed) will be described below as one example by referring to the drawings. FIG. 3 is a sectional view of an element showing the structure of the EEPROM (a storing element) disclosed in Patent Document 1. In the storing element shown in FIG. 3, a plurality of n type layers 10a, 10b and 10c are formed on a p type layer 5. Insulating films (oxide films) 6a, 6b and 8 and gate electrodes 7a, 7b and 9 are laminated and formed on a base. Then, the electrode 9 serves as a connecting terminal of a control word line 1, and the electrode 7a serves as a connecting terminal of a selecting word line 2. The n type layers 10a and 10b respectively function as a source 3 and a drain 4.
When data is written in the storing element, a boosted writing potential Vpp (=about 10 V) is applied to the control word line (a control gate) 1. A negative writing intermediate potential Veel (=about −5V) boosted negatively is applied to the P type layer 5, the source 3 and the drain 4. Thus, voltage of about 15V is applied to the thin oxide film 6b and electrons are injected to a floating gate 7b through the thin oxide film 6b. At this time, the potential of the word line (a selecting gate) 2 is set to an earth potential.
Further, when the data of the storing element is erased, a negatively boosted erasing potential Veeh (=about −10V) is applied to the control word line (the control gate) l and a positively boosted erasing potential Vpp (=about 10V) is applied to the P type layer 5. Thus, the electrons are pulled out from the floating gate 7b to the P type layer 5 through the thin oxide film 6b. At this time, the potential of the word line (the selecting gate) 2 is set to a source potential Vcc. The source 3 and the drain 4 are opened.
When the data is written and erased through the thin oxide film 6b, a channel full surface FN tunnel phenomenon is utilized. Thus, the data can be written and erased by low consumed power. Further, when the data of the storing element is read, the source potential Vcc is applied to the word line (the selecting gate) 2 on which the data is to be read, voltage of Vcc/2 about half as high as the source potential is applied to the drain 4, and further, the source 3 and the control word line (the control gate) 1 are grounded. Then, “0” data or “1” data are allowed to correspond to the different quantity of electric current supplied between the drain 4 and the source 3.
As described above, since the storing element does not need to generate high voltage by a boosting circuit upon reading the data, the storing element is suitable for a semiconductor storing element that requires a low consumed current operation such as the IC card.
FIG. 13 is a block diagram showing a structure of one example of a usual selecting word line driving circuit (a word line driver). In FIG. 13, to an address decoder 110, an operation start signal TRG (a reading operation or an erasing operation is performed by receiving the rise of the TRG signal), a READ signal for selecting an input signal upon reading operation, an ERASE signal for controlling an input signal upon erasing operation and an address signal AIN [m:0] are inputted.
The address decoder 110 generates control signals AB0 to ABn in accordance with the address signal AIN [m:0]. The word line driving circuit 120 (the word line driver) includes CMOS inverter drivers (word line driving element circuits) provided respectively correspondingly to word lines. The CMOS inverter drivers respectively comprise complementarily connected P channel MOS transistors (MP0 to MPn) and N channel MOS transistors (MN0 to MNn). The CMOS inverter drivers respectively receive control signals (AB-0 to AB-n) outputted from the address decoder 110 to selectively drive word lines (SWL0 to SWLn) corresponding to an operation mode.
The operation of the word line driving circuit constructed as described above will be described by referring to timing charts shown in FIGS. 14(a) and 14(b). FIG. 14(a) is the timing chart when a reading operation is performed. When the reading operation is carried out, the READ signal is firstly inputted to the address decoder 110 (time t80). Then, the address signal AIN[m:0] for designating an address in which the data is read is inputted (time t81).
At a timing when the TRG signal shifts from L to H (time t82), a signal for designating a selected word line of the word line control signals (AB-0 to AB-n) shifts from H to L (time t83). In FIG. 1, to designate the word line SWL0, an A-0 signal shifts from H to L.
When the control signal AB-0 shifts from H to L (time t83), the source potential is supplied to the word line SWL0 to perform the reading operation. At this time, the P channel MOS transistor MP0 and the N channel MOS transistor MN0 for driving the word line SWL0 are temporarily turned on at the same time and a through current is supplied from the source potential Vcc to an earth potential Vss. Further, to set the word line SWL0 to the source potential Vcc, a peak current is generated.
When the reading operation is completed and the TRG signal shifts from H to L (time t84), the word line control signal AB-0 shifts from L to H (time t85). Thus, the source potential of the word line SWL0 is changed to the earth potential Vss by the word line driving circuit 120.
In this process, the P channel MOS transistor MP0 and the N channel MOS transistor MN0 for driving the word line SWL0 are likewise temporarily turned on at the same time to supply the through current from the source potential Vcc to the earth potential Vss. Further, to drop the word line SWL0 to the earth potential Vss, the peak current is generated.
FIG. 14(b) is a timing chart when an erasing operation is performed. When the erasing operation is carried out, the ERASE signal is inputted to the address decoder 110 (time t90). When the ERASE signal is received, all of the word line control signals AB-0 to AB-n shift from H to L (time t91).
At this time, the source potential is supplied to all the word lines (SWL0 to SWLn) at the same time. During this process, in each of the CMOS inverter drivers for driving each of the word lines (SWL0 to SWLn), the P channel MOS transistor and the N channel MOS transistor are turned on at the same time to supply the through current from the source potential Vcc to the earth potential Vss. Further, to set all the word lines to the source potential Vcc, the peak current is generated.
Further, when the erasing operation is completed, the ERASE signal shifts from L to H (time t92) and all the word line control signals (AB-0 to AB-n) shift from H to L (time t93). Then, the potentials of all the word lines (SWL0 to SWLn) shift to the earth potential Vss.
At this time, in each of the CMOS inverter drivers, the through current likewise flows, and the peak current is generated in accordance with the change of the potentials of all the word lines (SWL0 to SWLn) from the source potential Vcc to the earth potential Vss.
A technique for reducing the through current or the peak current is disclosed in, for instance, Patent Document 2. According to this technique, load MOS transistors are provided in a plurality of output buffer circuits to limit an electric current. Thus, when the plurality of CMOS output buffers are simultaneously operated to invert outputs, a quantity of electric current supplied to each of the CMOS output buffers is limited to entirely reduce a through current during a transition response operation.
[Patent Document 1]JP-A-11-177068[Patent Document 2]JP-2000-124782
According to a technique disclosed in the Patent Document 2, a gate of a load transistor is always opened, so that a through current cannot be completely eliminated. Further, this technique is limited to an output buffer circuit and cannot be applied to a case in which loads (the number of word lines as objects to be driven) are different depending on a reading mode or an erasing mode like a word line driving circuit as an object of the present invention.
Specifically, in an EEPROM, a source potential Vcc needs to be applied to a word line to be read upon reading. Further, data stored in a storing element within a prescribed period needs to be read. To rapidly set the potential of the word line to the source potential Vcc, a transistor having a capacity capable of supplying an electric current as much as possible is required. However, when the transistor having a high capacity capable of supplying a large quantity of electric current is used for a transistor for driving the word line, the quantity of the through current is also undesirably increased.
Further, during an erasing operation, the potentials of all word lines connected to all storing elements need to be set to the source potential Vcc. As soon as the erasing operation is started, the source potential Vcc is supplied to all the word lines at once. Thus, in the word line driving circuits for driving the word lines, the through current is simultaneously supplied and the electric current is abruptly supplied to all the word lines. Accordingly, a large quantity of peak current is generated. At that time, the source potential is lowered to cause a risk of generating a malfunction of a semiconductor storage device.
As described above, in order to meet a demand for a high speed reading operation, it is difficult to make the use of the transistor high in its current supplying capability compatible with the suppression of the through current or the peak current.